Performance optimization using exact sensitization

Authors:
Alexander Saldanha;Heather Harkness;Patrick C. McGeer;Robert K. Brayton;Alberto L. Sangiovanni-Vincentelli
Affiliations:
Cadence Berkeley Labs, Berkeley, CA;Digital Equipment Corporation, Hudson, MA and University of California, Berkeley, CA;Cadence Berkeley Labs, Berkeley, CA;University of California, Berkeley, CA;University of California, Berkeley, CA
Venue:
DAC '94 Proceedings of the 31st annual Design Automation Conference
Year:
1994

Circuit structure relations to redundancy and delay: the KMS algorithm revisited

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circuit enhancement by eliminating long false paths

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance optimization of digital circuits

Performance optimization of digital circuits
Exploiting multi-cycle false paths in the performance optimization of sequential circuits

ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors

Logic clause analysis for delay optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A delay model for logic synthesis of continuously-sized networks

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Speeding up technology-independent timing optimization by network partitioning

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing sequential cycles through Shannon decomposition and retiming

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Timing-driven optimization using lookahead logic circuits

Proceedings of the 46th Annual Design Automation Conference
Global delay optimization using structural choices

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Masking timing errors on speed-paths in logic circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Fixed points for multi-cycle path detection

Proceedings of the Conference on Design, Automation and Test in Europe
Delay optimization using SOP balancing

Proceedings of the International Conference on Computer-Aided Design

Hi-index	0.00