Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Circuit structure relations to redundancy and delay: the KMS algorithm revisited
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient sum-to-one subsets algorithm for logic optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Is redundancy necessary to reduce delay?
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing the initial states of retimed circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact minimum cycle times for finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automated multi-cycle symbolic timing verification of microprocessor-based designs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance optimization using exact sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
False path exclusion in delay analysis of RTL-based datapath-controller designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elimination of multi-cycle false paths by state encoding
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Functional clock schedule optimization
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Efficient identification of multi-cycle false path
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Fixed points for multi-cycle path detection
Proceedings of the Conference on Design, Automation and Test in Europe
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