Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circuit delay models and their exact computation using Timed Boolean Functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Elimination of multi-cycle false paths by state encoding
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
| Hi-index | 0.00 |