Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Circuit delay models and their exact computation using Timed Boolean Functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Exact minimum cycle times for finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
On the interaction of functional and timing behaviour of combinational logic circuits
On the interaction of functional and timing behaviour of combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
Functional timing analysis made fast and general
Proceedings of the 49th Annual Design Automation Conference
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
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A SAT-based modeling for event propagation in gate-level digital circuits, which is used for accurate calculation of critical delay in combinational and sequential circuits, is presented in this article. The accuracy of the critical delay estimation process depends on the accuracy with which the circuit in operation is modeled. A high level of precision in the modeling of the internal events in a circuit for the sake of greater accuracy causes a combinatorial blowup in the size of the problem, resulting in a scalability bottleneck for which most existing techniques effect a trade-off by restricting themselves to less precise models. SAT based techniques have a good track record in efficiency and scalability when the problem sizes become too large for most other methods. This article proposes a SAT-based technique for symbolic event propagation within a circuit which facilitates the estimation of the critical delay of circuits with a greater degree of accuracy, while at the same time scaling efficiently to large circuits. We report very encouraging results on the ISCAS85 and ISCAS89 benchmark circuits using the proposed technique.