Circuit delay models and their exact computation using Timed Boolean Functions
DAC '93 Proceedings of the 30th international Design Automation Conference
Exact minimum cycle times for finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance optimization under rise and fall parameters
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
On the interaction of functional and timing behaviour of combinational logic circuits
On the interaction of functional and timing behaviour of combinational logic circuits
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
On the problem of gate assignment under different rise and fall delays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path sensitization in critical path problem [logic circuit design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a SAT based technique for timing analysis by an accurate modeling of event propagation within gate-level circuits. The accuracy of the result depends on the level of detail with which circuit activity is modeled. However, the combinatorial blowup in the size and complexity of the problem is the main bottleneck in any detailed modeling. The proposed technique overcomes this problem by an efficient SAT modeling of events at the nodes of the circuit which scales very smoothly with increase in size of the circuit without sacrificing on accuracy even with industry standard gate delays of 0.01ns granularity. This improvement in performance enables the modeling of more complex gate delay models like the rise/fall delay model which can simulate circuit activity more realistically than the fixed gate delay model.