Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bounded delay timing analysis and power estimation using SAT
Microelectronics Journal
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
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Present-day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching, and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures the complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths, as well as conditions for such situations. This information is then represented as an event-time graph. A temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A binary decision diagram-based implementation of this system has been made. Results on the International Symposium on Circuits and Systems (ISCAS)85 benchmarks are presented