Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic model checking using SAT procedures instead of BDDs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Towards true crosstalk noise analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switching window computation for static timing analysis in presence of crosstalk noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
The Manic Depression of Microprocessor Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Eliminating False Positives in Crosstalk Noise Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
RESTA: a robust and extendable symbolic timing analysis tool
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate timing analysis using SAT and pattern-dependent delay models
Proceedings of the conference on Design, automation and test in Europe
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Pitfalls in delay fault testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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Debugging and speed-binning a fabricated design requires a pattern-dependent timing model to generate patterns, which static timing analysis is incapable of providing. To address these issues, we propose a timing analysis tool that integrates a pattern-dependent delay model into its analysis. Our approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a satisfiability (SAT) solver. We generate a critical path and input vectors that stimulate it, taking into account pattern-dependent effects such as data-dependent gate delays and multiple-inputs switching. The effectiveness and validity of the proposed methodology is illustrated through experiments on various benchmark circuits and comparisons directly with SPICE.