A high-frequency custom CMOS S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent Fault Detection in Random Combinational Logic
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Intelligible Test Techniques to Support Error-Tolerance
ATS '04 Proceedings of the 13th Asian Test Symposium
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
A Framework for Architecture-Level Lifetime Reliability Modeling
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Multi-vector tests: a path to perfect error-rate testing
Proceedings of the conference on Design, automation and test in Europe
Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Critical Path Selection for Delay Test Considering Coupling Noise
ETS '08 Proceedings of the 2008 13th European Test Symposium
Incremental SAT Instance Generation for SAT-based ATPG
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
ATS '09 Proceedings of the 2009 Asian Test Symposium
Overcoming Early-Life Failure and Aging for Robust Systems
IEEE Design & Test
Compacting test vector sets via strategic use of implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Threshold testing: improving yield for nanoscale VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Journal of Electronic Testing: Theory and Applications
Zchaff2004: an efficient SAT solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this article, we will investigate the diagnostic capability of logic implications to identify possible failure locations when an error is detected online. We will then utilize this information to select a highly efficient test set that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.