Systematic Unidirectional Error-Detecting Codes
IEEE Transactions on Computers
Fault-tolerance design of the IBM Enterprise System/9000 Type 9021 processors
IBM Journal of Research and Development
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
IEEE Transactions on Computers
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Algorithm level re-computing: a register transfer level concurrent error detection technique
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
Journal of Electronic Testing: Theory and Applications
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Diversity Techniques for Concurrent Error Detection
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A combinatorial group testing method for FPGA fault location
ACST'06 Proceedings of the 2nd IASTED international conference on Advances in computer science and technology
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
IEEE Transactions on Computers
Dependable design technique for system-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Non-linear Error Detection for Finite State Machines
Information Security Applications
Improving the testability and reliability of sequential circuits with invariant logic
Proceedings of the 20th symposium on Great lakes symposium on VLSI
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Autonomic fault-handling and refurbishment using throughput-driven assessment
Applied Soft Computing
Low-cost fault-tolerant switch allocator for network-on-chip routers
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A comparative cost/security analysis of fault attack countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Consensus-Based evaluation for fault isolation and on-line evolutionary regeneration
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
An emerging threat: eve meets a robot
INTRUST'10 Proceedings of the Second international conference on Trusted Systems
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Self-healing reconfigurable logic using autonomous group testing
Microprocessors & Microsystems
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
Journal of Electronic Testing: Theory and Applications
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
| Hi-index | 0.01 |
Concurrent error detection (CED) techniques (based onhardware duplication, parity codes, etc.) are widely used toenhance system dependability. All CED techniquesintroduce some form of redundancy. Redundant systems aresubject to common-mode failures (CMFs). While most ofthe studies of CED techniques focus on area overhead, fewanalyze the CMF vulnerability of these techniques. In thispaper, for the first time, we present simulation results toquantitatively compare various CED schemes based ontheir area overhead and the protection (data integrity) theyprovide against multiple failures and CMFs. Our resultsindicate that, for the simulated combinational logiccircuits, although diverse duplex systems (with twodifferent implementations of the same logic function)sometimes have marginally higher area overhead, theyprovide significant protection against multiple failures andCMFs compared to other CED techniques like parityprediction.