Proceedings of the third session on Reliability in VLSI circuits : operation, manufacturing and design: operation, manufacturing and design
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Digital System Design with VHDL
Digital System Design with VHDL
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Exploiting Idle Cycles for Algorithm Level Re-Computing
Proceedings of the conference on Design, automation and test in Europe
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
RT level reliability enhancement by constructing dynamic TMRS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
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There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered within the optimisation process of iterative, cost function-driven high-level synthesis, such that on-line testing resources are inserted automatically without any modification of the source HDL code. This involves the introduction of a metric for on-line testability. A variation of duplication testing (namely inversion testing) is also used, providing the system with an additional degree of freedom towards minimising hardware overheads associated with test resource insertion. Considering on-line testability within the synthesis process facilitates fast and efficient design space exploration, resulting in a versatile high-level synthesis process, capable of producing alternative realisations according to the designerýs directions.