On the optimum checkpoint selection problem
SIAM Journal on Computing
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
IEEE Transactions on Computers
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
EURO-DAC '94 Proceedings of the conference on European design automation
Phantom redundancy: a high-level synthesis approach for manufacturability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Synthesizing Fast, Online-Testable Control Units
IEEE Design & Test
Automatic Synthesis of Self-Recovering VLSI Systems
IEEE Transactions on Computers
High Level Synthesis Techniques for Efficient Built-In-Self Repair
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A tool for automatic generation of self-checking data paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
IEEE Transactions on Computers
RT level reliability enhancement by constructing dynamic TMRS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Improving chip multiprocessor reliability through code replication
Computers and Electrical Engineering
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We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection. Introspection uses idle computation cyles in the data path and idle data transfer cycles in the interconnection network in a synergistic fashion for concurrent error detection and diagnosis (CEDD). The resulting on-chip fault latencies are one ten-thousandth (10-4) of previously reported system level concurrent error detection and diagnosis latencies. The associated area overhead and performance penalty are negligible. We derive a cost function that considers introspection constraints such as (i) executing an operation on three disjoint function units for diagnosis and (ii) promoting function units to participate in at least one CEDD operation. We formulate integration of introspection constraints into the operation-to-operator binding phase of high-level synthesis as a weighted bipartite matching problem. The effectiveness of introspection and its implementation are illustrated on numerous industrial strength benchmarks.