Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
An iterative improvement algorithm for low power data path synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High level synthesis for reconfigurable datapath structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Allocation and Binding During Fault-Secure Microarchitecture Synthesis
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
IEEE Transactions on Computers
A technique for micro-rollback self-recovery synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithm level re-computing: a register transfer level concurrent error detection technique
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
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We address the problem of synthesizing fault-secure controller/data path circuits from behavioral specifications. We use an iterative improvement based behavioral synthesis framework that performs module selection, clock selection, scheduling, and resource sharing with the aim of minimizing the area of the synthesized circuit, while allowing multicycling, chaining, and module pipelining. We present a dynamic comparison selection algorithm that can be used during behavioral synthesis to determine which intermediate results in the computation need to be secured in order to enable maximal resource sharing. Previous work on synthesizing fault-secure data paths has focused on ensuring that aliasing cannot occur in any part of the design. We demonstrate that such an approach can lead to unnecessarily large overheads. In order to alleviate the overheads incurred for fault security, our behavioral synthesis framework uses aliasing probability analysis (ALPS) in order to identify resource sharing configurations that reduce area, while introducing a very low probability of aliasing (of the order of 10/sup -10/ for a bitwidth of 32) in the resultant data path. We report experimental results for several behavioral descriptions that demonstrate the efficacy of our techniques in synthesizing fault-secure controller/datapaths with low overheads.