Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
| Hi-index | 0.04 |
The problem and efficient solution of automated synthesis of a self-recovery chip using micro-rollback and checkpoint insertion techniques are proposed and discussed. An efficient design of micro-rollback and checkpoint insertion can be achieved by considering them during the scheduling and allocation steps. The rollback and recovery scheme is designed to satisfy the constraints on the number of registers available and the maximum allowable recovery time. The proposed checkpointing (rollback point) algorithm will allow the system to recover from most transient faults