High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Rollback and Recovery Strategies for Computer Programs
IEEE Transactions on Computers
A technique for micro-rollback self-recovery synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithm level re-computing: a register transfer level concurrent error detection technique
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IEEE Transactions on Computers
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We address optimization problems arising in the synthesis of application specific integrated circuits (ASICs) that recover from transient faults via a rollback and retry approach. In this approach, each segment of a computation is duplicated and the results are compared using comparators. If the compared values are unequal, the computation is rolled back to the beginning of the segment (rollback point) and retried. Previous work in this area has generally been of an experimental nature focusing on heuristic approaches. We examine these problems from an algorithmic perspective. Several comparison and rollback strategies for reducing hardware costs and the delay caused by a transient fault have been previously proposed. For various combinations of these comparison and rollback strategies, we present efficient algorithms to analyze a given design to determine the maximum delay that can be caused by a transient fault of a given duration. These algorithms are based on formal characterizations of when a transient fault can cause a maximum delay for each combination of comparison and rollback strategies. We have also developed an efficient algorithm for designing fault-tolerant datapaths under hardware and delay constraints.