Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Design of Concurrent Error-Detectable VLSI-Based Array Dividers
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Error-Correcting Goldschmidt Dividers Using Time Shared TMR
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
High Level Synthesis Techniques for Efficient Built-In-Self Repair
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient time redundancy for error correcting inner-product units and convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault tolerant Newton-Raphson dividers using time shared TMR
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A 32-Bit Risc Processor with Concurrent Error Detection
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Proceedings of the conference on Design, automation and test in Europe
| Hi-index | 0.00 |
Re-computing with Shifted Operands (RESO) is a logic leveltime redundancy based concurrent error detection (CED)technique.In RESO, logic level operations (and, nand, ete)are carried out twice - once on the basic input and once on the sifted input.Result from these two operations are comparedto detect an error.Although using RESO operators in registertransfer level (RTL) designs is straightforward, its entails timeand area overhead.We developed an RT level CED techniquecalled Algorithm level Re-computing with Shifted Operands (ARESO).ARESO does not use specialized RESO operators.Rather, it exploits RT level scheduling, pipelining, operator chaining, and multi-cycling to incorporate user specifiederrors detection latencies.ARESO supports hardware vs.performance vs. error detection latency trade-offs.ARESOhad been validated on practical design examples using Synopsys Behavior Compiler