Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Design of Concurrent Error-Detectable VLSI-Based Array Dividers
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Error-Correcting Goldschmidt Dividers Using Time Shared TMR
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
High Level Synthesis Techniques for Efficient Built-In-Self Repair
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Efficient time redundancy for error correcting inner-product units and convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault tolerant Newton-Raphson dividers using time shared TMR
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A 32-Bit Risc Processor with Concurrent Error Detection
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
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In this paper we propose an algorithm-level time redundancybased CED scheme that exploits the hardware allocationdiversity at the Register Transfer (RT) level. Although thenormal computation and the re-computation are carried outon the same data path, the operation-to-operator allocationfor the normal computation is different from the operation-to-operatorallocation for the re-computation. We show thatproposed scheme provides very good CED capability withvery low area overhead.