Error Correction by Alternate-Data Retry
IEEE Transactions on Computers
Partially Self-Checking Circuits and Their Use in Performing Logical Operations
IEEE Transactions on Computers
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
Time redundant fault-location in bit-sliced ALU's
IEEE Transactions on Computers
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Efficient time redundancy for error correcting inner-product units and convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
IEEE Transactions on Computers
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Proceedings of the conference on Design, automation and test in Europe
Compiler-assisted soft error detection under performance and energy constraints in embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Instruction-Level Fault Tolerance Configurability
Journal of Signal Processing Systems
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
LUT-based FPGA technology mapping for reliability
Proceedings of the 47th Design Automation Conference
Concurrent off-phase built-in self-test of dormant logic
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Concurrent error detection architectures for field multiplication using gaussian normal basis
ISPEC'10 Proceedings of the 6th international conference on Information Security Practice and Experience
Comprehensive analysis of software countermeasures against fault attacks
Proceedings of the Conference on Design, Automation and Test in Europe
A low-power instruction replay mechanism for design of resilient microprocessors
ACM Transactions on Embedded Computing Systems (TECS)
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A new method of concurrent error detection in the Arithmetic and Logic Units (ALU's) is proposed. This method, called "Recomputing with Shifted Operands" (RESO), can detect errors in both the arithmetic and logic operations. RESO uses the principle of time redundancy in detecting the errors and achieves its error detection capability through the use of the already existing replicated hardware in the form of identical bit slices. It is shown that for most practical ALU implementations, including the carry-lookahead adders, the RESO technique will detect all errors caused by faults in a bit-slice or a specific subcircuit of the bit slice. The fault model used is more general than the commonly assumed stuck-at fault model. Our fault model assumes that the faults are confined to a small area of the circuit and that the precise nature of the faults is not known. This model is very appropriate for the VLSI circuits.