High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Computer arithmetic algorithms
Computer arithmetic algorithms
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
IEEE Transactions on Computers
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Carry checking/parity prediction adders and ALUs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards fault tolerant parallel prefix adders in nanoelectronic systems
Proceedings of the conference on Design, automation and test in Europe
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Journal of Electronic Testing: Theory and Applications
Towards scalable arithmetic units with graceful degradation
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, a methodology for the development of fault-tolerant adders based on the Radix 2 Signed Digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free” property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.