IEEE Transactions on Computers
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
An Interpolating Memory Unit for Function Evaluation: Analysis and Design
IEEE Transactions on Computers
IEEE Transactions on Computers
Representational and Denotational Semantics of Digital Systems
IEEE Transactions on Computers
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
IEEE Transactions on Computers - Special issue on computer arithmetic
IEEE Transactions on Computers
Redundant Integer Representations and Fast Exponentiation
Designs, Codes and Cryptography - Special issue dedicated to Gustavus J. Simmons
Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
Technology Scaling Effects on Multipliers
IEEE Transactions on Computers
A new parallel multiplication algorithm and its VLSI implementation
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
New Efficient Structure for a Modular Multiplier for RNS
IEEE Transactions on Computers
Signed Digit Addition and Related Operations with Threshold Logic
IEEE Transactions on Computers
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
Optimal Left-to-Right Binary Signed-Digit Recoding
IEEE Transactions on Computers - Special issue on computer arithmetic
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
IEEE Transactions on Computers
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
IEEE Transactions on Computers
Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I/sup 2/L Technology
IEEE Transactions on Computers
Division Using a Logarithmic-Exponential Transform to Form a Short Reciprocal
IEEE Transactions on Computers
Integration, the VLSI Journal
VLSI Implementation of Modulo Multiplication Using Carry Free Addition
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms
Journal of VLSI Signal Processing Systems
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
IEEE Transactions on Computers
Real-Time Systems
IEEE Transactions on Computers
Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop
Analog Integrated Circuits and Signal Processing
Low power robust signal processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
On the distribution of runs of ones in binary strings
Computers & Mathematics with Applications
Compact non-binary fast adders using single-electron devices
Microelectronics Journal
An efficient signed digit montgomery multiplication for RSA
Journal of Systems Architecture: the EUROMICRO Journal
A new redundant binary booth encoding for fast 2n-bit multiplier design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A Novel Redundant Binary Number to Natural Binary Number Converter
Journal of Signal Processing Systems
Vector-matrix multiplication based on a ternary optical computer
HPCA'09 Proceedings of the Second international conference on High Performance Computing and Applications
Hi-index | 15.03 |
A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.