A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL

• Authors:

• Hirofumi Sakamoto;Ken'ichiro Uda;Bu-Y. Lee;Hiroyuki Ochi;Kazao Taki;Takao Tsuda

• Affiliations:

• Dept. of Computer Engineering, Hiroshima City University, Asaminami-ku, Hiroshima, 731-3194, Japan;Dept. of Computer and Systems Engineering, Kobe University, Nada-ku, Kobe, 657-8501, Japan;Dept. of Computer and Systems Engineering, Kobe University, Nada-ku, Kobe, 657-8501, Japan;Dept. of Computer Engineering, Hiroshima City University, Asaminami-ku, Hiroshima, 731-3194, Japan;Dept. of Computer and Systems Engineering, Kobe University, Nada-ku, Kobe, 657-8501, Japan;Dept. of Computer Engineering, Hiroshima City University, Asaminami-ku, Hiroshima, 731-3194, Japan

• Venue:
• ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
• Year:
• 2000