High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
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Abstract: We show that a 3-valued current mode CMOS 2-input BSC adder can be converted into a CMOS binary 4-2 counter or into a 1-digit Avizienis-like adder using a redundant number representation. Using a current mode algorithm to derive binary CMOS implementations of these arithmetic operators leads to equivalent or faster circuit implementation than the typical implementations that have been used until now.