High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
IEEE Transactions on Computers
A hardwired generalized algorithm for generating the logarithm base-k by iteration
IEEE Transactions on Computers
Introduction to numerical analysis: 2nd edition
Introduction to numerical analysis: 2nd edition
FOCUS microcomputer number system
Communications of the ACM
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
IEEE Transactions on Computers
IEEE Transactions on Computers
Powering by a Table Look-Up and a Multiplication with Operand Modification
IEEE Transactions on Computers
Error Analysis of the Kmetz/Maenner Algorithm
Journal of VLSI Signal Processing Systems
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
A Gaussian Noise Generator for Hardware-Based Simulations
IEEE Transactions on Computers
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation
Journal of Signal Processing Systems
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A technique for the evaluation of a general continuous function f(x) is presented, and the design of an interpolating memory as an implementation of the technique is described. The technique partitions the domain of f(x) into segments and defines an interpolating (or approximating) function for each. The implementation is a memory subsystem that holds the parameters of the approximating functions and yields an interpolated function value on each read reference. Polynomial interpolating functions are considered in particular. Hardware requirements (memory and computational logic) are analyzed in terms of the required precision. It is shown that as long as f(x) has d+1 derivatives, where d is the degree of the interpolating polynomial, d+1 additional bits of precision of the computed f(x) are obtained for each additional address bit used in the interpolating memory. This establishes a tradeoff between memory and computational logic, which can be exploited in the design of a unit for a specific function, for any precision requirement. Furthermore, a single unit can be designed for any class of functions that have the required derivatives. Two examples of implementations for particular functions are presented.