Stochastic simulation
Goodness-of-fit techniques
An Interpolating Memory Unit for Function Evaluation: Analysis and Design
IEEE Transactions on Computers
A fast normal random number generator
ACM Transactions on Mathematical Software (TOMS)
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The Monty Python method for generating random variables
ACM Transactions on Mathematical Software (TOMS)
A Comparison of Methods for Generating Normal Deviates on Digital Computers
Journal of the ACM (JACM)
Journal of the ACM (JACM)
Automatic sampling with the ratio-of-uniforms method
ACM Transactions on Mathematical Software (TOMS)
Normal Random Numbers: Using Machine Analysis to Choose the Best Algorithm
ACM Transactions on Mathematical Software (TOMS)
A comparison of multivariate normal generators
Communications of the ACM
A fast procedure for generating normal random variables
Communications of the ACM
Design of High Speed AWGN Communication Channel Emulator
Analog Integrated Circuits and Signal Processing
Faithful Bipartite ROM Reciprocal Tables
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
High-Performance Architectures for Elementary Function Generation
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
A Hardware Gaussian Noise Generator for Channel Code Evaluation
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Continuous random variate generation by fast numerical inversion
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Parameterized High Throughput Function Evaluation for FPGAs
Journal of VLSI Signal Processing Systems
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Art of Error Correcting Coding
The Art of Error Correcting Coding
Approximate-min* constraint node updating for LDPC code decoding
MILCOM'03 Proceedings of the 2003 IEEE conference on Military communications - Volume I
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis
IEEE Transactions on Computers
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Journal of VLSI Signal Processing Systems
Gaussian random number generators
ACM Computing Surveys (CSUR)
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A compact and accurate Gaussian variate generator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
IEEE Transactions on Communications
Design and FPGA implementation an accurate real time 3x4 MIMO channel emulator
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A hardware gaussian noise generator using the wallace method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hierarchical segmentation for hardware function evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.99 |
Hardware simulation offers the potential of improving code evaluation speed by orders of magnitude over workstation or PC-based simulation. We describe a hardware-based Gaussian noise generator used as a key component in a hardware simulation system, for exploring channel code behavior at very low bit error rates (BERs) in the range of 10^{-9} to 10^{-10}. The main novelty is the design and use of nonuniform piecewise linear approximations in computing trigonometric and logarithmic functions. The parameters of the approximation are chosen carefully to enable rapid computation of coefficients from the inputs while still retaining high fidelity to the modeled functions. The output of the noise generator accurately models a true Gaussian Probability Density Function (PDF) even at very high \sigma values. Its properties are explored using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test, and 2) an application for decoding of Low-Density Parity-Check (LDPC) codes. An implementation at 133MHz on a Xilinx Virtex-II XC2V4000-6 FPGA produces 133 million samples per second, which is seven times faster than a 2.6GHz Pentium-IV PC; another implementation on a Xilinx Spartan-IIE XC2S300E-7 FPGA at 62MHz is capable of a three times speedup. The performance can be improved by exploiting parallelism: An XC2V4000-6 FPGA with nine parallel instances of the noise generator at 105MHz can run 50 times faster than a 2.6GHz Pentium-IV PC. We illustrate the deterioration of clock speed with the increase in the number of instances.