Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation
IEEE Transactions on Computers
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
The Symmetric Table Addition Method for Accurate Function Approximation
Journal of VLSI Signal Processing Systems
Hardware Designs for Exactly Rounded Elementary Functions
IEEE Transactions on Computers
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
IEEE Transactions on Computers
Fast Evaluation of the Elementary Functions in Single Precision
IEEE Transactions on Computers
Function Evaluation by Table Look-up and Addition
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
High-speed double precision computation of nonlinear functions
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Symmetric Bipartite Tables for Accurate Function Approximation
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
"Partially Rounded" Small-Order Approximations for Accurate, Hardware-Oriented, Table-Based Methods
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
High-Performance Architectures for Elementary Function Generation
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Realization of Multiple-Output Functions by Reconfigurable Cascades
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A method to decompose multiple-output logic functions
Proceedings of the 41st annual Design Automation Conference
Minimization of fractional wordlength on fixed-point conversion for high-level synthesis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Gaussian Noise Generator for Hardware-Based Simulations
IEEE Transactions on Computers
IEEE Transactions on Computers
Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design Methods for Multiple-Valued Input Address Generators
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
Optimal Curve Fitting With Piecewise Linear Functions
IEEE Transactions on Computers
On the optimization of heterogeneous MDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
On the number of segments needed in a piecewise linear approximation
Journal of Computational and Applied Mathematics
A special-purpose compiler for look-up table and code generation for function evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
A dynamic non-uniform segmentation method for first-order polynomial function evaluation
Microprocessors & Microsystems
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
| Hi-index | 14.98 |
This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA).