Whirlpool PLAs: a regular logic structure and their synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
Design Methods of Radix Converters Using Arithmetic Decompositions
IEICE - Transactions on Information and Systems
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Abstract: A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA. This realization uses time domain multiplexing, and is useful for the case where the number of output pins is limited.