Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
IEEE Design & Test
Spectral Techniques for Technology Mapping
Spectral Techniques for Technology Mapping
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking of datapaths based on canonical arithmetic expressions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Efficient construction of binary moment diagrams for verifying arithmetic circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synthesis by spectral translation using Boolean decision diagrams
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
PHDD: an efficient graph representation for floating point circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
IEEE Transactions on Computers
IEEE Transactions on Computers
Word-level decision diagrams, WLCDs and division
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Polynomial methods for component matching and verification
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Polynomial methods for allocating complex components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioral synthesis of combinational logic using spectral-based heuristics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Decision Diagram Method for Calculation of Pruned Walsh Transform
IEEE Transactions on Computers
Streaming BDD manipulation for large-scale combinatorial problems
Proceedings of the conference on Design, automation and test in Europe
Spectral decision diagrams using graph transformations
Proceedings of the conference on Design, automation and test in Europe
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Checking equivalence for partial implementations
Proceedings of the 38th annual Design Automation Conference
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Polynomial circuit models for component matching in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Ordered binary decision diagrams
Logic Synthesis and Verification
IEEE Transactions on Computers
A Unifying Approach to Edge-valued and Arithmetic Transform Decision Diagrams
Automation and Remote Control
On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division
Formal Methods in System Design
Limits of Using Signatures for Permutation Independent Boolean Comparison
Formal Methods in System Design
Factored Edge-Valued Binary Decision Diagrams
Formal Methods in System Design
Arithmetic Boolean Expression Manipulator Using BDDs
Formal Methods in System Design
Multi-Terminal Binary Decision Diagrams: An Efficient DataStructure for Matrix Representation
Formal Methods in System Design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Formal Verification Using Edge-Valued Binary Decision Diagrams
IEEE Transactions on Computers
Verifying integrity of decision diagrams
Integration, the VLSI Journal
Minimization of word-level decision diagrams
Integration, the VLSI Journal
Advances in Model Representations
PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Modleing and Checking Networks of Communicating Real-Time Process
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Information and Computation - Special issue: LICS'97
Handbook of automated reasoning
Symbolic Verification and Analysis of Discrete Timed Systems
Formal Methods in System Design
Formal Verification of Combinational Circuit
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Mathematical framework for representing discrete functions as word-level polynomials
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improved Boolean function hashing based on multiple-vertex dominators
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Constructing efficient formal models from high-level descriptions using symbolic simulation
International Journal of Parallel Programming
Statistical probabilistic model checking with a focus on time-bounded properties
Information and Computation
Numerical Function Generators Using LUT Cascades
IEEE Transactions on Computers
Functionally linear decomposition and synthesis of logic circuits for FPGAs
Proceedings of the 45th annual Design Automation Conference
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Approximate transient analysis of large stochastic models with WinPEPSY-QNS
Computer Networks: The International Journal of Computer and Telecommunications Networking
Planning and execution with phase transitions
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 2
A transform-parametric approach to Boolean matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Model checking using SMT and theory of lists
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Testability analysis and behavioral testing of the Hopfield neural paradigm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic linkage analysis algorithms and their implementation
Transactions on Computational Systems Biology III
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