Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Modified branching programs and their computational power
Modified branching programs and their computational power
Finding the Optimal Variable Ordering for Binary Decision Diagrams
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Spectral transforms for large boolean functions with applications to technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Zero-suppressed BDDs for set manipulation in combinatorial problems
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '94 Proceedings of the 31st annual Design Automation Conference
The implicit set paradigm: a new approach to finite state system verification
Formal Methods in System Design - Special issue on symbolic model checking
Efficient OBDD-based boolean manipulation in CAD beyond current limits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Verification of arithmetic circuits with binary moment diagrams
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal Methods in System Design
Improving the Variable Ordering of OBDDs Is NP-Complete
IEEE Transactions on Computers
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Linear sifting of decision diagrams
DAC '97 Proceedings of the 34th annual Design Automation Conference
Sampling schemes for computing OBDD variable orderings
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Using lower bounds during dynamic BDD minimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Speeding up symbolic model checking by accelerating dynamic variable reordering
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Accessibility of information on the Web
intelligence
Lazy group sifting for efficient symbolic state traversal of FSMs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Algorithms and Data Structures in VLSI Design
Algorithms and Data Structures in VLSI Design
Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams
ISAAC '93 Proceedings of the 4th International Symposium on Algorithms and Computation
Frontiers of Feasible and Probabilistic Feasible Boolean Manipulation with Branching Programs
STACS '93 Proceedings of the 10th Annual Symposium on Theoretical Aspects of Computer Science
On the Descriptive and Algorithmic Power of Parity Ordered Binary Decision Diagrams
STACS '97 Proceedings of the 14th Annual Symposium on Theoretical Aspects of Computer Science
On the Existence of Polynomial Time Approximation Schemes for OBDD Minimization (Extended Abstract)
STACS '98 Proceedings of the 15th Annual Symposium on Theoretical Aspects of Computer Science
Sample Method for Minimization of OBDDs
SOFSEM '98 Proceedings of the 25th Conference on Current Trends in Theory and Practice of Informatics: Theory and Practice of Informatics
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Speeding up variable reordering of OBDDs
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Probabilistic Verification of Multiple-Valued Functions
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Three-Dimensional Feedforward Neural Networks and Their Realization by Nano-Devices
Artificial Intelligence Review
Three-dimensional feedforward neural networks and their realization by nano-devices
Artificial intelligence in logic design
Decomposition of systems of Boolean functions determined by binary decision diagrams
Journal of Computer and Systems Sciences International
Approximate model-based diagnosis using preference-based compilation
SARA'05 Proceedings of the 6th international conference on Abstraction, Reformulation and Approximation
Minimization of binary decision diagrams for systems of incompletely defined Boolean functions
Journal of Computer and Systems Sciences International
| Hi-index | 0.00 |
Ordered Binary Decision Diagrams (OBDDs) play a key role in the automated synthesis and formal verification of digital systems. They are the state-of-the-art data structure for representing switching functions in various branches of electronic design automation. In the following we discuss the properties of this data structure, characterize its algorithmic behavior, and describe some prominent applications.