Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Functional Decomposition with Application to FPGA Synthesis
Functional Decomposition with Application to FPGA Synthesis
Algorithms and Data Structures in VLSI Design
Algorithms and Data Structures in VLSI Design
Ordered binary decision diagrams
Logic Synthesis and Verification
Boolean Decomposition Using Two-literal Divisors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A BDD-based fast heuristic algorithm for disjoint decomposition
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computers
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
Proceedings of the 45th annual Design Automation Conference
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
OBDD-based function decomposition: algorithms and implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimization of binary decision diagrams for systems of incompletely defined Boolean functions
Journal of Computer and Systems Sciences International
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A method for the decomposition of systems of completely defined Boolean functions given a two-block partition of the set of variables and a decision algorithm for the partition of this set are proposed. The system of functions is determined by a binary decision diagram, which simplifies the search for the variable partition and the decomposition based on this partition. Results of experimental studies demonstrating the efficiency of the proposed decomposition in the synthesis of logic circuits are presented.