Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Timed shared circuits: a power-efficient design style and synthesis tool
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic Synthesis and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Optimizing sequential cycles through Shannon decomposition and retiming
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Projecting Sums of Products
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
The complexity of modular decomposition of Boolean functions
Discrete Applied Mathematics - Special issue: Boolean and pseudo-boolean funtions
Timing-driven logic bi-decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An approximation algorithm for cofactoring-based synthesis
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Decomposition of systems of Boolean functions determined by binary decision diagrams
Journal of Computer and Systems Sciences International
Synthesis of P-circuits for logic restructuring
Integration, the VLSI Journal
Minimization of P-circuits using Boolean relations
Proceedings of the Conference on Design, Automation and Test in Europe
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits
Proceedings of the Conference on Design, Automation and Test in Europe
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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We investigate restructuring techniques based on decomposition/factorization, with the objective to move critical signals toward the output while minimizing area. A specific application is synthesis for minimum switching activity (or high performance), with minimum area penalty, where decompositions with respect to specific critical variables are needed (the ones of highest switching activity for example). In this paper we describe new types of factorization that extend Shannon cofactoring and are based on projection functions that change the Hamming distance of the original minterms and on appropriate don't care sets, to favor logic minimization of the component blocks. We define two new general forms of decomposition that are special cases of the pattern F = G(H(X), Y). The related implementations, called P-Circuits, show experimentally promising results in area with respect to Shannon cofactoring.