Two-level logic minimization: an overview
Integration, the VLSI Journal
On a New Boolean Function with Applications
IEEE Transactions on Computers
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
Multi-level logic optimization
Logic Synthesis and Verification
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Three-Level Decomposition with Application to PLDs
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
ISMVL '99 Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic
Approximability and completeness in the polynomial hierarchy
Approximability and completeness in the polynomial hierarchy
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An efficient heuristic approach to solve the unate covering problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-level logic minimization based on function regularities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for OR-AND-OR synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity of two-level logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testability of SPP Three-Level Logic Networks in Static Fault Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
SOP restructuring by exploiting don't cares
Microprocessors & Microsystems
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We propose a new algebraic four-level expression called k-EXOR-projected sum of products (kEP-SOP). The optimization of a kEP-SOP is NPNP-hard, but can be approximated within a fixed performance guarantee in polynomial time. Moreover, fully testable circuits under the stuck-at-fault model can be derived from kEP-SOPs by adding at most a constant number of multiplexer gates. The experiments show that the computational time is very short and the results are most of the time optimal with respect to the number of products involved. kEP-SOPs also prove experimentally a good starting point for general multilevel logic synthesis.