Two-level logic minimization: an overview
Integration, the VLSI Journal
On a New Boolean Function with Applications
IEEE Transactions on Computers
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
ISMVL '99 Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic
An efficient heuristic approach to solve the unate covering problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for OR-AND-OR synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
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Multi-level logic synthesis yields much more compact expressions of a given Boolean function with respect to standard two-level sum of products (SOP) forms. On the other hand, minimizing an expression with more than two-levels can take a large time. In this paper we introduce a novel algebraic four-level expression, named k-EXOR-projected sum of products (kEP-SOP) form, whose synthesis can be performed in polynomial time with an approximation algorithm starting from a minimal SOP. Our experiments show that the resulting networks can be obtained in very short computational time and often exhibit a high quality. We also study the testability of these networks under the Stuck-at-fault model, and show how fully testable circuits can be generated from them by adding at most a constant number of multiplexer gates.