An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Dimension-reducible Boolean functions based on affine spaces
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. We conjecture that, when n is sufficiently large, an EX-SOP for n-bit adder requires at most 2**n products while an ordinary sum-of-products expression (SOP) requires 6(2**n)-4n-5 products. Experimental results for two- and four-valued benchmark functions show that the proposed method produces better EX-SOPs than existing methods.