Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On a New Boolean Function with Applications
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Logical Design of Digital Systems
Logical Design of Digital Systems
Synthesis for Testability: Binary Decision Diagrams
STACS '92 Proceedings of the 9th Annual Symposium on Theoretical Aspects of Computer Science
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
ISMVL '99 Proceedings of the Twenty Ninth IEEE International Symposium on Multiple-Valued Logic
A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Efficient minimization of fully testable 2-SPP networks
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An approximation algorithm for fully testable kEP-SOP networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
On the Construction of Small Fully Testable Circuits with Low Depth
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
A fast algorithm for OR-AND-OR synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of SPP three-level logic networks using affine spaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple-Valued Minimization for PLA Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testability of SPP Three-Level Logic Networks in Static Fault Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Compact area, low delay and good testability properties are important optimization goals in the synthesis of circuits for Boolean functions. Unfortunately, these goals typically contradict each other. Multi-level circuits are often quite small but can have a long delay, due to their unbounded number of levels. On the other hand, circuits with low depth guarantee low delay but are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.