On the construction of small fully testable circuits with low depth
Microprocessors & Microsystems
Advances in Engineering Software
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 50th Annual Design Automation Conference
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This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm, Espresso-EXACT, for minimization of multiple-valued input, binary-valued output logic functions. Minimization of these functions is an important step in the optimization of programmable logic arrays (PLA's). In particular, the problems of two-level multiple-output minimization, minimization of PLA's with input decoders and solutions to the input encoding problem rely on efficient solutions to the multiple-valued minimization problem. Results are presented for a large class of PLA's taken from actual chip designs. These results show that the heuristic algorithm Espresso-MV comes very close to producing optimum solutions for most of the examples. Also, results from a chip design in progress at Berkeley show how important multiple-valued minimization can be for PLA optimization.