Core-Based Scan Architecture for Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Stimulus generation for constrained random simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
In-System Silicon Validation and Debug
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe
Functional coverage measurements and results in post-Silicon validation of Core2 duo family
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Built-in functional tests for silicon validation and system integration of telecom SoC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiple-Valued Minimization for PLA Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
In-system constrained-random stimuli generation for post-silicon validation
ITC '12 Proceedings of the 2012 IEEE International Test Conference (ITC)
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Linear Feedback Shift Registers (LFSRs) have been extensively used for compressed manufacturing test. They have been recently employed as a foundation for porting constrained-random stimuli from a pre-silicon verification environment to in-system validation. This work advances this concept by improving both the hardware efficiency and the duration of in-system validation experiments.