Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A machine program for theorem-proving
Communications of the ACM
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Building Circuits from Relations
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Generating random solutions for constraint satisfaction problems
Eighteenth national conference on Artificial intelligence
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
Proceedings of the 2005 international symposium on Physical design
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Towards efficient sampling: exploiting random walk strategies
AAAI'04 Proceedings of the 19th national conference on Artifical intelligence
Simplifying Boolean constraint solving for random simulation-vector generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of Formal Word-Level Analysis to Constrained Random Simulation
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
Automatic constraint generation for guided random simulation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SAT-based semiformal verification of hardware
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Generating diverse solutions in SAT
SAT'11 Proceedings of the 14th international conference on Theory and application of satisfiability testing
Proceedings of the International Conference on Computer-Aided Design
QuteRTL: towards an open source framework for RTL design synthesis and verification
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
The system verification methodology for advanced TLM verification
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A robust general constrained random pattern generator for constraints with variable ordering
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 50th Annual Design Automation Conference
A scalable and nearly uniform generator of SAT witnesses
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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Constrained random simulation is the main workhorse in today's hardware verification flows. It requires the random generation of input stimuli that obey a set of declaratively specified input constraints, which are then applied to validate given design properties by simulation. The efficiency of the overall flow depends critically on (1) the performance of the constraint solver and (2) the distribution of the generated solutions. In this paper we discuss the overall problem of efficient constraint solving for stimulus generation for mixed Boolean/integer variable domains and propose a new hybrid solver based on Markov-chain Monte Carlo methods with good performance and distribution.