Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Counterexample-guided choice of projections in approximate symbolic model checking
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Constraint synthesis for environment modeling in functional verification
Proceedings of the 40th annual Design Automation Conference
Using a formal specification and a model checker to monitor and direct simulation
Proceedings of the 40th annual Design Automation Conference
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Proceedings of the 41st annual Design Automation Conference
A Framework for Constrained Functional Verification
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Linking Simulation with Formal Verification at a Higher Level
IEEE Design & Test
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
XFM: extreme formal method for capturing formal specification into abstract models
Formal methods and models for system design
System level design paradigms: Platform-based design and communication synthesis
Proceedings of the 41st annual Design Automation Conference
Test generation games from formal specifications
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Stimulus generation for constrained random simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Markov Chain Monte Carlo Sampler for Mixed Boolean/Integer Constraints
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
Computers and Electrical Engineering
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a functional coverage metric are all created automatically from a single specification. Additionally, the process exploits the structure of a specification written with simple style rules. The methodology was used to verify a large-scale I/O design from the Stanford FLASH project.