Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Principles of Verifiable RTL Design
Principles of Verifiable RTL Design
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Assertion-Based Design
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Constraint-Based Verification
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Introduction to Software Testing
Introduction to Software Testing
Using formal specifications to support testing
ACM Computing Surveys (CSUR)
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Model-driven test generation for system level validation
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
TAP'08 Proceedings of the 2nd international conference on Tests and proofs
Accelerating Assertion Coverage With Adaptive Testbenches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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With the emerging predominance of assertion-based dynamic verification, test generation is a key area where assertions can play a bigger role. Generation of test sequences from properties defined by assertions can help in finding failures in corner-cases of the design specification that without assertions may not be possible. As such, we rely on the duality between property checkers and test generators to take advantage of the information present in the assertions for effective test scenarios--a much needed endeavor given the increasing challenges in verification. To undertake such an effort, we first elaborate on the relation between the coverage of the assertion-based specification and the specific coverage metrics over finite nondeterministic automata representing the assertions. We finally present Airwolf-TG that generate test sequences from compact automata produced by the MBAC tool.