CESC: a visual formalism for specification and verification of SoCs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Exception handling in microprocessors using assertion libraries
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
TheoSim: combining symbolic simulation and theorem proving for hardware verification
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IP Quality: A Design, Not a Verification Problem
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Exploiting PSL standard assertions in a theorem-proving-based verification environment
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Refactoring digital hardware designs with assertion libraries
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
IEEE Transactions on Computers
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
System on Chips optimization using ABV and automatic generation of SystemC codes
Microprocessors & Microsystems
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design and Deployment of Large-Scale Software-Intensive Systems in Urban Districts
Software-Intensive Systems and New Computing Paradigms
Assertion-based dynamic verification for executable UML specifications
ACS'08 Proceedings of the 8th conference on Applied computer scince
MYGEN: automata-based on-line test generator for assertion-based verification
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Exploiting "architecture for verification" to streamline the verification process
Proceedings of the 46th Annual Design Automation Conference
An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
Computers and Electrical Engineering
Automated design debugging with abstraction and refinement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Journal of Electronic Testing: Theory and Applications
Validating assertion language rewrite rules and semantics with automated theorem provers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Vacuity analysis for property qualification by mutation of checkers
Proceedings of the Conference on Design, Automation and Test in Europe
GoldMine: automatic assertion generation using data mining and static analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Towards assertion-based verification of heterogeneous system designs
Proceedings of the Conference on Design, Automation and Test in Europe
Formal semantics for PSL modeling layer and application to the verification of transactional models
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Model-driven design and validation of embedded software
Proceedings of the 6th International Workshop on Automation of Software Test
A case for runtime validation of hardware
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Dynamic property mining for embedded software
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A testbench specification language for SystemC verification
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Word level feature discovery to enhance quality of assertion mining
Proceedings of the International Conference on Computer-Aided Design
Model checking of global power management strategies in software with temporal logic properties
Proceedings of the 6th India Software Engineering Conference
Generating concise assertions with complete coverage
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Enabling dynamic assertion-based verification of embedded software through model-driven design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A guiding coverage metric for formal verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic refinement of requirements for verification throughout the SoC design flow
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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From the Publisher:"The focus of Assertion-Based Design is three-fold: How to specify assertions; How to create and adopt a methodology that supports assertion-based design (predominately for RTL design); and What to do with the assertions and methodology once you have them." To support these three over-arching goals, the authors showcase multiple forms of assertion specification: Accellera Open Verification Library (OVL), Accellera Property Specification Language (PSL), and Accellera System Verilog.