Model checking
Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Assertion-Based Design
Model checking of analog systems using an analog specification language
Proceedings of the conference on Design, automation and test in Europe
Review: Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal
Instrumenting AMS assertion verification on commercial platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Proceedings of the 46th Annual Design Automation Conference
Checking temporal properties of discrete, timed and continuous behaviors
Pillars of computer science
Hi-index | 0.00 |
In this paper a comprehensive assertion-based verification methodology for the digital, analog and software domain of heterogeneous systems is presented. The proposed methodology combines a novel mixed-signal assertion language and the corresponding automatic verification algorithm. The algorithm translates the heterogeneous temporal properties into observer automata for a semi-formal verification. This enables automatic verification of complex heterogeneous properties that can not be verified by existing approaches. The experimental results show the integration of mixed-signal assertions into a simulation environment and demonstrate the broad applicability and the high value of the evolved solution.