Specifying real-time properties with metric temporal logic
Real-Time Systems
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Theoretical Computer Science
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Journal of the ACM (JACM)
Synthesizing Monitors for Safety Properties
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
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CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
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FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Proceedings of the Conference on Logic of Programs
Logics and Models of Real Time: A Survey
Proceedings of the Real-Time: Theory in Practice, REX Workshop
A compositional approach to CTL* verification
Theoretical Computer Science - Formal methods for components and objects
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Logics for Real Time: Decidability and Complexity
Fundamenta Informaticae - Continuous Time Paradigms in Logic and Automata
On the complexity of omega -automata
SFCS '88 Proceedings of the 29th Annual Symposium on Foundations of Computer Science
Testing Conformance of Real-Time Applications by Automatic Generation of Observers
Electronic Notes in Theoretical Computer Science (ENTCS)
Analog Circuit Verification: a State of an Art
Electronic Notes in Theoretical Computer Science (ENTCS)
On synthesizing controllers from bounded-response properties
CAV'07 Proceedings of the 19th international conference on Computer aided verification
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Approximation, sampling and voting in hybrid computing systems
HSCC'06 Proceedings of the 9th international conference on Hybrid Systems: computation and control
Real time temporal logic: past, present, future
FORMATS'05 Proceedings of the Third international conference on Formal Modeling and Analysis of Timed Systems
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
HVC '08 Proceedings of the 4th International Haifa Verification Conference on Hardware and Software: Verification and Testing
Requirements Validation for Hybrid Systems
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Amir Pnueli and the dawn of hybrid systems
Proceedings of the 13th ACM international conference on Hybrid systems: computation and control
On simulation-based probabilistic model checking of mixed-analog circuits
Formal Methods in System Design
Towards assertion-based verification of heterogeneous system designs
Proceedings of the Conference on Design, Automation and Test in Europe
Robust satisfaction of temporal logic over real-valued signals
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Weighted lumpability on markov chains
PSI'11 Proceedings of the 8th international conference on Perspectives of System Informatics
Parametric identification of temporal properties
RV'11 Proceedings of the Second international conference on Runtime verification
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Validation of requirements for hybrid systems: A formal approach
ACM Transactions on Software Engineering and Methodology (TOSEM)
On temporal logic and signal processing
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
Efficient robust monitoring for STL
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We survey some of the problems associated with checking whether a given behavior (a sequence, a Boolean signal or a continuous signal) satisfies a property specified in an appropriate temporal logic and describe two such monitoring algorithms for the real-time logic MITL.