Artificial Intelligence
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Model checking
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
CMSB '08 Proceedings of the 6th International Conference on Computational Methods in Systems Biology
Robustness of temporal logic specifications for continuous-time signals
Theoretical Computer Science
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Checking temporal properties of discrete, timed and continuous behaviors
Pillars of computer science
Analog property checkers: a DDR2 case study
Formal Methods in System Design
Robust satisfaction of temporal logic over real-valued signals
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
S-taliro: a tool for temporal logic falsification for hybrid systems
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Breach, a toolbox for verification and parameter synthesis of hybrid systems
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
On temporal logic and signal processing
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
Mining requirements from closed-loop control models
Proceedings of the 16th international conference on Hybrid systems: computation and control
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Monitoring transient behaviors of real-time systems plays an important role in model-based systems design. Signal Temporal Logic (STL) emerges as a convenient and powerful formalism for continuous and hybrid systems. This paper presents an efficient algorithm for computing the robustness degree in which a piecewise-continuous signal satisfies or violates an STL formula. The algorithm, by leveraging state-of-the-art streaming algorithms from Signal Processing, is linear in the size of the signal and its implementation in the Breach tool is shown to outperform alternative implementations.