Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
The benefits of relaxing punctuality
Journal of the ACM (JACM)
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
The Temporal Rover and the ATG Rover
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
A Verification System for Transient Response of Analog Circuits Using Model Checking
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Model checking of analog systems using an analog specification language
Proceedings of the conference on Design, automation and test in Europe
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
Test coverage for continuous and hybrid systems
CAV'07 Proceedings of the 19th international conference on Computer aided verification
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
Temporal logic verification using simulation
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Formal verification of phase-locked loops using reachability analysis and continuization
Proceedings of the International Conference on Computer-Aided Design
Realtime regular expressions for analog and mixed-signal assertions
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Parametric identification of temporal properties
RV'11 Proceedings of the Second international conference on Runtime verification
On temporal logic and signal processing
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
Efficient robust monitoring for STL
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems.In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach.