Quantitative temporal reasoning
Real-Time Systems
Model checking algorithms for analog verification
Proceedings of the 39th annual Design Automation Conference
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
A Verification System for Transient Response of Analog Circuits Using Model Checking
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Verifying analog oscillator circuits using forward/backward abstraction refinement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms
Electronic Notes in Theoretical Computer Science (ENTCS)
Analog property checkers: a DDR2 case study
Formal Methods in System Design
Towards assertion-based verification of heterogeneous system designs
Proceedings of the Conference on Design, Automation and Test in Europe
Formal approaches to analog circuit verification
Proceedings of the Conference on Design, Automation and Test in Europe
Combining time and frequency domain specifications for periodic signals
RV'11 Proceedings of the Second international conference on Runtime verification
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the International Conference on Computer-Aided Design
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction
Proceedings of the Conference on Design, Automation and Test in Europe
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
In this contribution an advanced methodology for model checking of analog systems is introduced. A new Analog Specification Language (ASL) for efficient property specifications is defined and model checking algorithms for implementing this language are presented. This allows verification of complex static and dynamic circuit properties like Oscillation and Startup Time that have not yet been formally verifiable with previous approaches. The new verification methodology is applied to example circuits and experimental results are discussed and compared to conventional circuit simulation.