Formal approaches to analog circuit verification

Authors:
Erich Barke;Darius Grabowski;Helmut Graeb;Lars Hedrich;Stefan Heinen;Ralf Popp;Sebastian Steinhorst;Yifan Wang
Affiliations:
Leibniz Universitaet Hannover, Germany;Leibniz Universitaet Hannover, Germany;Technische Universitaet Muenchen, Germany;Goethe University of Frankfurt/Main, Germany;RWTH Aachen University, Germany;edacentrum GmbH, Germany;Goethe University of Frankfurt/Main, Germany;RWTH Aachen University, Germany
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

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Abstract

For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key technology for efficient design flows. However, industrial availability of formal methods for analog circuit verification is still negligible despite a growing need. In recent years, research institutions have made considerable advances in the area of formal verification of analog circuits. This paper presents a selection of four recent approaches in analog verification that cover a broad scope of verification philosophies.