Formal verification of analog circuits in the presence of noise and process variation

Authors:
Rajeev Narayanan;Behzad Akbarpour;Mohamed H. Zaki;Sofiène Tahar;Lawrence C. Paulson
Affiliations:
Concordia University, Montreal, Quebec, Canada;Concordia University, Montreal, Quebec, Canada;University of British Columbia, Vancouver, British Columbia, Canada;Concordia University, Montreal, Quebec, Canada;University of Cambridge, Cambridge, UK
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose to use stochastic differential equations (SDE) to model the designs. We find a closed form solution for the SDEs, then integrate the device variation due to the 0.18μm fabrication process and verify properties using MetiTarski. We illustrate the proposed approach on an inverting Op-Amp Integrator and a Band-Gap reference bias circuit.