Formal verification of SoC based embedded design using context based assertions

  • Authors:

  • Chandrasekaran Subramaniam;Prasanna Vertivel;Srinath Badri;Sriram Badri

  • Affiliations:

  • Rajalakshmi Engineering College, Anna University, Chennai, India;Easwari Engineering College, Anna University, Chennai, India;Easwari Engineering College, Anna University, Chennai, India;Sri Venkateswara College of Engineering, Anna University, Chennai, India

  • Venue:
  • CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
  • Year:
  • 2011

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Abstract

The objective of the work is to propose a formal verification logic for mixed mode hardware using the internal and external settings of the circuits towards context based assertions. The mixed signal hardware needed for an artificial arm using a programmable system on chip (pSoC) micro controller is verified and developed. The earlier CTL and LTL use the path quantifiers and logical operators to formally verify the behaviour of the system in all possible future behaviour respectively. An extension to the existing layered approach of the verification mechanism, a context layer may be added to fulfil the mode requirement verification of the hardware circuits along with the value driven timely behaviour verification. The MAD (Mixed Analog Digital) circuits that are realized using system on chip (SoC) device are verified using the proposed Hybrid Context Mode (HCM) Logic and verified using the Model Verifier, Alloy. The proposed logic simplifies the model checking and property checking strategies of the individual MAD circuits with the context based assertion technique.