DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Nontree routing for reliability and yield improvement [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Concurrent wire spreading, widening, and filling
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2008 international workshop on System level interconnect prediction
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Statistical Parameter Identification of Analog Integrated Circuit Reverse Models
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Circuits and Systems II: Express Briefs
Formal verification of analog circuits in the presence of noise and process variation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (6σ). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.