A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Authors:
Shien-Chun Luo;Lih-Yih Chiou
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

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Abstract

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitIines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.