A 2.6 μW sub-threshold mixed-signal ECG SoC

Authors:
Steven C. Jocke;Jonathan F. Bolus;Stuart N. Wooters;Travis N. Blalock;Benton H. Calhoun
Affiliations:
University of Virginia, Charlottesville, VA, USA;University of Virginia, Charlottesville, VA, USA;University of Virginia, Charlottesville, VA, USA;University of Virginia, Charlottesville, VA, USA;University of Virginia, Charlottesville, VA, USA
Venue:
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Year:
2009

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Cited 1

A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

IEEE Transactions on Circuits and Systems II: Express Briefs

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Abstract

This paper describes a 130 nm CMOS sub-threshold (sub-VT) mixed-signal system-on-chip (SoC) that acquires and processes an electrocardiogram (ECG) signal for wireless ECG monitoring. Low power ECG devices permit continuous monitoring for longer durations between power recharging. Co-designing the digital and analog blocks creates opportunities for reducing power at the system level. The SoC uses a sub-threshold digital microcontroller (μC) for adaptive control of the sub-VT biased analog components and for processing the ECG data. The μC operates from 0.24 V to 1.2 V and consumes as little as 1.51 pJ per instruction. The SoC consumes only 2.6 μW while providing raw ECG data or processed heart rate data, which can lower the wireless data rate by 500X.